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文章提出了一种符合IEEE Std.1596.3-1996标准,适用于片间高速低压差分信号LVDS(Low Voltage Differential Signal)传输的接收器芯片设计方案,有效地解决了传统的接口电路在低电源电压低功耗的条件下无法满足高速数字信号传输的问题。方案采用新型的轨到轨折叠式共源共栅前置预放大器拓展了接收器的共模范围以及独立的电流源电路为系统提供偏置并通过CSMC 0.5μm工艺流片,在各个工艺角下对接收器芯片进行了直流分析、交流分析和瞬态分析。仿真结果表明,此芯片满足设计指标,在共模电平为±1V的误差范围内,具有100mV的阈值迟滞,最高数据传输速率大于200 Mbps。
This paper presents a design of a receiver chip that meets the IEEE Std.1596.3-1996 standard and is suitable for transmitting Low Voltage Differential Signal (LVDS) signals between chips. It effectively solves the problem that the traditional interface circuit has low power supply voltage Under the conditions of power consumption can not meet the high-speed digital signal transmission problems. The new rail-to-rail folded cascode preamplifier extends the receiver’s common-mode range and independent current source circuitry to bias the system through the CSMC 0.5μm process flow chip, Receiver chip for DC analysis, exchange analysis and transient analysis. The simulation results show that the chip meets the design specifications and has a threshold hysteresis of 100mV at a common-mode level of ± 1V with a maximum data transfer rate greater than 200 Mbps.