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为了提高能量回收电路的效率,提出了能量回收电容耦合逻辑电路。该电路的非绝热损失与门的复杂度和负载均无关,其大小只决定于电路中逻辑门的数目。利用电容耦合,而不是开关逻辑网络进行逻辑求值,相对减小了导通电阻和绝热损失。该电路在电路形式上降低了功耗,在结构设计中,采取阈值逻辑结构,使功耗和性能优化。基于TSMC0.35μm工艺,设计了4位加法器,并和4位的2N-2N2P加法器、静态CMOS加法器进行比较。Hspice仿真表明:该电路电路功耗只有2N-2N2P的46%,静态CMOS的20%~31%。该电路与传统的CMOS电路比较,能耗大大降低。
In order to improve the efficiency of the energy recovery circuit, an energy recovery capacitor-coupled logic circuit is proposed. The circuit’s non-adiabatic loss is independent of gate complexity and load, and its size depends only on the number of logic gates in the circuit. Using capacitive coupling rather than switching logic networks for logic evaluation results in a relatively reduced on-resistance and adiabatic loss. The circuit reduces the power consumption in the circuit form, in the structural design, the threshold logic structure to optimize power consumption and performance. Based on the TSMC0.35μm process, a 4-bit adder is designed and compared with a 4-bit 2N-2N2P adder and a static CMOS adder. Hspice simulation shows that the power consumption of this circuit is only 46% of 2N-2N2P and 20% ~ 31% of that of static CMOS. The circuit compared with the traditional CMOS circuit, greatly reducing energy consumption.