论文部分内容阅读
基于中国科学院微电子研究所的0.8μm标准N阱CMOS工艺以及ISETCAD软件,模拟了具有加长LDD结构的高压CMOS器件。器件的击穿电压可以达到30V以上。加长的LDD结构是通过非自对准的源漏注入实现的。LDD区域的长度和该区域的掺杂浓度对器件击穿影响很大。对于不同的工作电压(10-20V),实验给出了相应的LDD区域长度和该区域的注入剂量。只需要在标准工艺的基础上增加三层掩模版和相应的工艺步骤就能实现低高压工艺的兼容。而且对称结构和非对称结构(具有更大的驱动电流)器件都能实现。与LDMOS或DDDMOS工艺相比,节省了成本,而且所设计的高压器件尺寸较小,有利于集成。
Based on the 0.8μm standard N-well CMOS process and the ISETCAD software of Institute of Microelectronics, Chinese Academy of Sciences, a high-voltage CMOS device with an extended LDD structure was modeled. Breakdown voltage of the device can reach more than 30V. The extended LDD structure is implemented by non-self-aligned source and drain implantations. The length of the LDD region and the doping concentration in this region greatly affect device breakdown. For different operating voltage (10-20V), the experiment gives the corresponding LDD region length and injection dose in this region. Only need to add three layers of reticle and the corresponding process steps on the basis of the standard process can realize the compatibility of low pressure process. And symmetrical structure and asymmetric structure (with a larger drive current) devices can be achieved. Compared with the LDMOS or DDDMOS process, the cost savings and the small size of the high-voltage device designed make for integration.