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A low-power,configurable auto-gain control loop for a digital hearing aid system on a chip(SoC) is presented.By adopting a mixed-signal feedback control structure and peak detection and judgment,it can work in automatic gain or variable gain control modes through a digital signal processing unit.A noise-reduction and dynamic range(DR) improvement technique is also used to ensure the DR of the circuit in a low-voltage supply.The circuit is implemented in an SMIC 0.13 μm 1P8M CMOS process.The measurement results show that in a 1 V power supply,1.6 kHz input frequency and 200 mVp-p,the SFDR is 74.3 dB,the THD is 66.1 dB,and the total power is 89 μW,meeting the application requirements of hearing aid SoCs.
A low-power, configurable auto-gain control loop for a digital hearing aid system on a chip (SoC) is presented. By adopting a mixed-signal feedback control structure and peak detection and judgment, it can work in automatic gain or variable gain control modes through a digital signal processing unit. A noise-reduction and dynamic range (DR) improvement technique is also used to ensure the DR of the circuit in low-voltage supply. The circuit is implemented in an SMIC 0.13 μm 1P8M CMOS process The measurement results show that in a 1 V power supply, 1.6 kHz input frequency and 200 mVp-p, the SFDR is 74.3 dB, the THD is 66.1 dB, and the total power is 89 μW, meeting the application requirements of hearing aid SoCs.