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随着计算机新技术的发展,计算机的逻辑结构越来越复杂。逻辑设计中的错误也就越来越难免。要缩短机器的调试周期,必须在机器装配之前尽量减少逻辑设计中的错误,逻辑模拟是借助计算机来进行逻辑校验的有效手段。数字网络的逻辑模拟一般可分为寄存器传输级模拟和门级(动能级)模拟二类。本文主要讨论寄存器级模拟,门级模拟另文讨论。
With the development of new computer technologies, the logical structure of computers becomes more and more complicated. The errors in the logic design are also more and more inevitable. To shorten the commissioning cycle of the machine, you must minimize errors in the logic design before the machine is assembled, and logical simulation is an effective means of verifying the logic with a computer. Logic simulation of digital network can be divided into register transfer level simulation and gate level (kinetic energy level) simulation two categories. This article focuses on register-level simulation, another discussion of gate-level simulation.