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针对超大规模集成电路低功耗设计技术市场需求的迅速增大,提出了一种新的百万门级系统芯片低功耗设计流程,重点分析了芯片系统级、电路级、逻辑级与物理级四个不同的层次的低功耗设计方法,包括系统构架、时钟与功耗管理算法等低功耗关键技术。以某新型雷达SoC低功耗设计为例,采用SMIC 0.18μm 1P6M CMOS工艺进行设计,版图尺寸为7.825 mm×7.820mm,规模约为200万门。实验结果表明,在100MHz工作频率下,采用新的低功耗设计流程后,前端设计阶段功耗降低了42.79%,后端设计阶段功耗降低了12.77%,芯片总功耗仅为350 mW。样品电路通过了用户某新型相控阵雷达系统的应用验证,满足小型化和低功耗的要求。
Aiming at the rapid increase of market demand for low-power VLSI design technology, a new low-power design flow of a million-gate system chip is proposed. The system-level, circuit level, logic level and physical level Four different levels of low-power design methods, including system architecture, clock and power management algorithms and other low-power key technologies. Taking a low-power design of a new type of radar SoC as an example, the SMIC 0.18μm 1P6M CMOS process is used for the design. The layout size is 7.825 mm × 7.820 mm and the scale is about 2 million gates. The experimental results show that the power consumption of the front end design stage is reduced by 42.79% and the power consumption of the back end stage is reduced by 12.77%. The total chip power consumption is only 350 mW at the operating frequency of 100MHz with the new low power consumption design flow. The sample circuit passed user validation of a new phased array radar system to meet the needs of miniaturization and low power consumption.