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提出了一种支持双数据率的数据时钟恢复电路,对电路中的鉴相器、环路滤波器、压控振荡器等进行了详细的分析研究和设计。基于0.18μm CMOS工艺,在电源电压1.8V下对电路进行仿真。仿真结果显示,电路在2.7Gb/s和1.62Gb/s随机流下的抖动峰峰值分别为14ps和12ps,功耗为80mW。测试结果显示,时钟恢复电路在2.7Gb/s和1.62Gb/s随机流下的抖动峰峰值分别为38ps和27ps。
A data clock recovery circuit supporting double data rate is proposed. The phase detector, loop filter and voltage controlled oscillator in the circuit are analyzed and designed in detail. Based on a 0.18μm CMOS process, the circuit is simulated at a supply voltage of 1.8V. The simulation results show that the jitter peak-to-peak value of the circuit under random flow of 2.7Gb / s and 1.62Gb / s are respectively 14ps and 12ps, and the power consumption is 80mW. The test results show that the jitter peak-to-peak values of the clock recovery circuit at random rates of 2.7Gb / s and 1.62Gb / s are 38ps and 27ps respectively.