介绍了一种基于并行 FIFO存储结构、应用于 HDTV编码器测试信源和码流数据分析的收发电路。它以 PC机 AT总线插卡形式插于 PC机上 ,通过 PC机控制 ,完成高速数据的发送和接收。本文对其设计思想、功能、结构、特点以及局限性作了详细介绍。特别是为提高速度、存储规模、降低成本等而采取的一些设计手段作了进一步分析。最后给出了实验结果。 A parallel FIFO memory structure is introduced, which is applied to the transmitting and receiving circuit of HDTV encoder test source and bit stream data analysis. It is inserted in the form of PC AT bus card in the PC, through the PC control, complete high-speed data transmission and reception. This article gives a detailed introduction to its design, function, structure, characteristics and limitations. In particular, some design methods adopted to speed up, store scale and reduce costs are further analyzed. Finally, the experimental results are given.