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为制备符合铁电场效应晶体管（ＦＦＥＴ）及铁电存储二极管（ＦＭＤ）要求的高质量铁电薄膜，采用激光脉冲沉积方法（ＰＬＤ）制备了Ａｕ／ＰＺＴ／ｐ－Ｓｉ／Ａｕ 和Ａｕ／ＰＺＴ／ＢＩＴ／ｐ－Ｓｉ／Ａｕ 多层结构的两种铁电薄膜系统。分析表明，在不同的电压范围，起主导作用的导电机制不同：电压低于１Ｖ时，漏电流遵循欧姆定律，电压在２．２～３．０Ｖ时，空间电荷限制电流（ＳＣＬＣ）占主导地位。Ｉ－Ｖ 特性曲线的结果表明Ａｕ／ＰＺＴ／ＢＩＴ／ｐ－Ｓｉ／Ａｕ 结构比Ａｕ／ＰＺＴ／ｐ－Ｓｉ／Ａｕ 结构的漏电流密度低两个数量级，Ｉ－Ｖ 特性曲线回滞窗口增大０．３Ｖ，这说明ＰＺＴ铁电薄膜与Ｓｉ衬底之间加入ＢＩＴ铁电层有助于降低漏电流密度，增大Ｉ－Ｖ回线的回滞窗口
In order to prepare high quality ferroelectric thin films that meet the requirements of ferroelectric field effect transistors (FFETs) and ferroelectric memory diodes (FMDs), Au / PZT / p-Si / Au and Au / PZT / Two kinds of ferroelectric thin film system of BIT / p-Si / Au multilayer structure. The analysis shows that the conductive mechanisms that play a leading role in different voltage ranges are different: when the voltage is lower than 1V, the leakage current follows Ohm’s law, and the space charge-limited current (SCLC) dominates when the voltage is between 2.2V and 3.0V . The results of the I-V characteristic curve show that the leakage current density of the Au / PZT / BIT / p-Si / Au structure is two orders of magnitude lower than the Au / PZT / p-Si / Au structure and the hysteresis window of the I- 0.3V, indicating that adding BIT ferroelectric layer between the PZT ferroelectric thin film and the Si substrate can help reduce the leakage current density and increase the hysteresis window of the I-V loop