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采用铜互连工艺的先进芯片在封装过程中,铜互连结构中比较脆弱的低介电常数(k)介质层,容易因受到较高的热机械应力而发生失效破坏,出现芯片封装交互作用(CPI)影响问题。采用有限元子模型的方法,整体模型中引入等效层简化微小结构,对45 nm工艺芯片进行三维热应力分析。用该方法研究了芯片在倒装回流焊过程中,聚酰亚胺(PI)开口、铜柱直径、焊料高度和Ni层厚度对芯片Cu/低k互连结构低k介质层应力的影响。分析结果显示,互连结构中间层中低k介质受到的应力较大,易出现失效,与报道的实验结果一致;上述四个因素对芯片低k介质中应力影响程度的排序为:焊料高度>PI开口>铜柱直径>Ni层厚度。
Advanced Chip with Copper Interconnect Process In the packaging process, the relatively low dielectric constant k dielectric layer of the copper interconnect structure is susceptible to failure due to higher thermo-mechanical stresses and to chip-package interactions (CPI) impact problem. By using finite element model, the equivalent layer is introduced into the overall model to simplify the microstructure, and the thermal stress of 45 nm process chip is analyzed. The influence of polyimide (PI) opening, copper pillar diameter, solder height and Ni layer thickness on the stress of low-k dielectric layer of Cu / low-k interconnect chip was investigated by the proposed method during the flip-chip reflow process. The results show that the stresses on low-k dielectrics in the middle layer of the interconnection structure are large and prone to failure, which is consistent with the reported experimental results. The order of influence of above four factors on the stress in low-k dielectrics is that the solder height> PI opening> Copper pillar diameter> Ni layer thickness.