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本文在交织器的保奇偶特性方面进行改进,提出了基于二次同余映射的保奇偶对称交织器设计。二次同余映射,易于实现,通过平移半个周期即可实现对称性,以达到减少延时和节省存储资源的目的;保奇偶特性,可以避免删余过程带来的不等差保护,从而提高编译码性能。本文提出的交织器设计,改进了文献[3]在保奇偶特性方面的不足,可以在采用二次同余映射形成对称的同时,具备保奇偶特性,并提高了约0.4dB左右编译码性能,并且算法中的保奇偶结构具有一定的普适性,可以应用在不同的交织器结构中。
In this paper, we improve the preservative parity characteristics of interleavers, and propose the design of the preservative parity symmetric interleaver based on quadratic congruence mapping. Quadratic congruence mapping, easy to implement, can realize the symmetry by shifting half a cycle, so as to reduce the delay and save the storage resource. The parity function can avoid the unequal protection caused by the puncturing process Improve codec performance. The proposed interleaver design improves the shortcomings of [3] in Polarimetric evenness, and it can preserve the parity even while using symmetric quadratic congruence mapping, and enhances the performance of codec about 0.4dB. And the algorithm in the Paul parity structure has a certain degree of generality, can be applied to different interleaver structure.