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利用Cadence集成电路设计软件,基于SMIC 0.18μm 1P6M CMOS工艺,设计了一款2.488 Gbit/s三阶电荷泵锁相环型时钟数据恢复(CDR)电路。该CDR电路采用双环路结构实现,为了增加整个环路的捕获范围及减少锁定时间,在锁相环(PLL)的基础上增加了一个带参考时钟的辅助锁频环,由锁定检测环路实时监控频率误差实现双环路的切换。整个电路由鉴相器、鉴频鉴相器、电荷泵、环路滤波器和压控振荡器组成。后仿真结果表明,系统电源电压为1.8 V,在2.488 Gbit/s速率的非归零(NRZ)码输入数据下,恢复数据的抖动峰值为14.6 ps,锁定时间为1.5μs,功耗为60 mW,核心版图面积为566μm×448μm。
Based on the SMIC 0.18μm 1P6M CMOS technology, a 2.488 Gbit / s third-order charge pump PLL clocked data recovery (CDR) circuit is designed by using Cadence integrated circuit design software. In order to increase the capture range of the entire loop and reduce the lock-up time, the CDR circuit is implemented with a double-loop structure. An auxiliary frequency-locked loop with a reference clock is added to the phase-locked loop (PLL) Monitoring the frequency error to achieve double loop switching. The circuit consists of phase detector, phase frequency detector, charge pump, loop filter and voltage-controlled oscillator. The post-simulation results show that the system power supply voltage is 1.8 V and the jitter of the recovered data peaked at 14.6 ps at a non-return-to-zero (NRZ) code input of 2.488 Gbit / s with a lock time of 1.5 μs and a power consumption of 60 mW , The core layout area of 566μm × 448μm.