论文部分内容阅读
Through silicon via(TSV)-TSV coupling is detrimental to the performance of three-dimensional(3D)integrated circuits(ICs) with the major negative effect of introducing coupling noise.In order to obtain an accurate estimation of the coupling level from TSV-TSV in the early design stage,this paper first proposes an impedancelevel model of the coupling channel between TSVs based on a two-port network,and then derives the formula of the coupling coefficient to describe the TSV-TSV coupling effect.The accuracy of the formula is validated by comparing the results with 3D full-wave simulations.Furthermore,a design technique for optimizing the coupling between adjacent coupled signal TSVs is proposed.Through SPICE simulations,the proposed technique shows its feasibility to reduce the coupling noise for both a simple TSV-TSV circuit and a complicated circuit with more TSVs,and demonstrates its potential for designers in achieving the goal of improving the electrical performance of 3D ICs.
Through silicon via (TSV) -TSV coupling is detrimental to the performance of three-dimensional (3D) integrated circuits (ICs) with the major negative effect of introducing coupling noise. Order to obtain an accurate estimation of the coupling level from TSV- TSV in the early design stage, this paper first proposes an impedance level model of the coupling channel between TSVs based on a two-port network, and then derives the formula of the coupling coefficient to describe the TSV-TSV coupling effect. Accuracy of the formula is validated by comparing the results with 3D full-wave simulations. Fermentmore, a design technique for optimizing the coupling between adjacent coupled signal TSVs is proposed. Through SPICE simulations, the proposed technique shows its feasibility to reduce the coupling noise for both a simple TSV-TSV circuit and a complicated circuit with more TSVs, and demonstrates its potential for designers in achieving the goal of improving the electrical performance of 3D ICs.