A high gain wide dynamic range transimpedance amplifier for optical receivers

来源 :Journal of Semiconductors | 被引量 : 0次 | 上传用户:yumeng88888888888888
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As the front-end preamplifiers in optical receivers, transimpedance amplifiers(TIAs) are commonly required to have a high gain and low input noise to amplify the weak and susceptible input signal. At the same time, the TIAs should possess a wide dynamic range(DR) to prevent the circuit from becoming saturated by high input currents. Based on the above, this paper presents a CMOS transimpedance amplifier with high gain and a wide DR for 2.5 Gbit/s communications. The TIA proposed consists of a three-stage cascade pull push inverter,an automatic gain control circuit, and a shunt transistor controlled by the resistive divider. The inductive-series peaking technique is used to further extend the bandwidth. The TIA proposed displays a maximum transimpedance gain of 88.3 dB with the –3 dB bandwidth of 1.8 GHz, exhibits an input current dynamic range from 100 nA to10 mA. The output voltage noise is less than 48.23 nV/p Hz within the –3 dB bandwidth. The circuit is fabricated using an SMIC 0.18 m 1P6M RFCMOS process and dissipates a dc power of 9.4 mW with 1.8 V supply voltage. As the front-end preamplifiers in optical receivers, transimpedance amplifiers (TIAs) are often required to have a high gain and low input noise to amplify the weak and susceptible input signals. DR) to prevent the circuit from becoming saturated by high input currents. Based on the above, this paper presents a CMOS transimpedance amplifier with high gain and a wide DR for 2.5 Gbit / s communications. The TIA proposed consists of a three-stage cascade pull push inverter, an automatic gain control circuit, and a shunt transistor controlled by the resistive divider. The inductive-series peaking technique is used to further extend the bandwidth. The TIA proposed displays a maximum transimpedance gain of 88.3 dB with the -3 dB bandwidth of 1.8 GHz, exhibits an input current dynamic range from 100 nA to 10 mA. The output voltage noise is less than 48.23 nV / p Hz within the -3 dB bandwidth. The circuit is fabricated using an SMIC 0.18 m 1P6M RFCMOS process and dissipates a dc power of 9.4 mW with 1.8 V supply voltage.
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