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Y2000-62359-145 0018683现场可编程序门阵列与正则阵列测试=Testing FP-GAs and regular arrays[会,英]//Proceedings of theIEEE European Test Workshop(ETW99).—145～157(PC)本部分收入2篇论文。题名为:基于 SRAM 的FPGA 逻辑单元的测试配置极小化和 FPGA 的自动测试设计。
Y2000-62359-145 0018683 FIELD PROGRAMMABLE DOOR AND REGULAR ARRAY TESTED = Testing FP-GAs and regular arrays This section of the Proceedings of the IEEE European Test Workshop (ETW99) .- 145-157 (PC) Income 2 papers. Titled: Minimizing Test Configurations for FPGA-Based FPGA Logic Cells and Automated Test Design for FPGAs.