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银河TS 1嵌入式微处理器是国防科学技术大学计算机学院设计的 32位嵌入式微处理器 ,完全正向设计 ,具有自主版权 .在体系结构上采用RISC内核 ,六级流水线 ,具有独立的数据Cache和指令Cache .特别的 ,TS 1具有两个取指部件的动态指令调度机制 ,拥有面向嵌入式应用的向量处理机制 ,采用基于内容复制 /交换的寄存器窗口技术的中断处理机制 ,支持WISHBONEIP核互连接口规范 ,具有良好的扩展性 .本文主要介绍TS 1的RISC核心设计思想和关键实现技术 ,最后给出性能评测结果 .TS 1设计已经在Altera的FPGAEP2 0K4 0 0EBC上面得到了验证 ,主频可以达到 36 .7MHz.
Galaxy TS 1 embedded microprocessor is a 32-bit embedded microprocessor designed by the National University of Defense Technology computer science, fully forward design, with independent copyright. In the architecture using RISC core, six pipeline, with independent data Cache and In particular, TS 1 has a dynamic instruction scheduling mechanism with two instruction fetch parts, a vector processing mechanism for embedded applications, an interrupt processing mechanism based on a register window technique of content copy / exchange, a WISHBONEIP core interconnect Interface specification, with good scalability.This paper mainly introduces TS1 RISC core design ideas and key implementation techniques, and finally gives the performance evaluation results.TS1 design has been verified in Altera’s FPGAEP2 0K4 0 0EBC above, the clock speed can Reached 36 .7MHz.