当前,集成电路正在向超大规模集成电路发展,预期在1985年到1990年间超大规模集成电路设计中将采用线宽为1至0.5微米的电路几何图形加工工艺(即亚微米工艺).这将使电路成本大大下降,例如采用2微米线条,存储器每位成本为3200微美分,采用1.5微米线条,成本为1925微美分,采用0.5微米 Currently, integrated circuits are being developed for very large scale integrated circuits and it is expected that circuit geometry processing (ie, sub-micron processing) with line widths of 1 to 0.5 micrometers will be used in VLSI designs between 1985 and 1990. This will enable Circuit costs have dropped drastically, for example with 2-micron lines, memory costs of 3200 micro-cents per bit, 1.5-micron lines at 1925 micro-cents, 0.5-micron