逐次逼近型模数转换器主要由电容阵列、比较器和数字控制电路组成。传统的数字控制电路保存一位数据时,需要依次经过移位和锁存两个步骤,因此每位数据的延迟约为两个D触发器的延迟时间,制约了转换速度。通过优化数字控制电路的移位寄存方式,使移位和寄存两个步骤只间隔一个与门的延迟时间,每次移位寄存的总延迟降低为一个D触发器和一个与门的延时之和,提高了转换速度。仿真分析表明,改进的逻辑结构延迟较传统结构降低了约28%。 Successive approximation analog-digital converter is mainly composed of capacitor array, comparator and digital control circuit. Traditional digital control circuit to save a data, you need to go through the shift and latch in two steps, so each data delay is about two D flip-flop delay, restricting the conversion speed. By optimizing the shift register method of the digital control circuit, the shift and register steps are separated by only one AND gate delay time, and the total delay of each shift register is reduced to one D flip-flop and one AND gate delay And, improve the conversion speed. Simulation analysis shows that the delay of the improved logic structure is reduced by about 28% compared with the traditional structure.