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研究了数字集成电路测试过程中的功耗问题,提出一种新的测试向量重排序方法,有效地减小了测试过程中电路状态的翻转次数。该方法根据电路结构和测试集的特征计算输入的影响度系数,定义加权海明距离,在不影响故障覆盖率的前提下,有效地降低了测试功耗。实验结果显示,经过该方法重排序后的测试集在测试过程中功耗平均降低48.07%,明显优于海明距离法。
The problem of power consumption in the digital IC testing process is studied. A new test vector reordering method is proposed, which can effectively reduce the number of flip-flops of the circuit during the test. According to the characteristics of the circuit structure and the test set, the method calculates the influence coefficient of the input and defines the weighted Hamming distance, which effectively reduces the test power consumption without affecting the fault coverage. Experimental results show that the power consumption of the test set after reordering is reduced by 48.07% on average during the test, which is obviously better than the Hamming distance method.