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在高速实时或非实时信号处理系统当中,为了实现对数据缓存必须要使用大容量存储器。由于SDRAM具有的诸多优点,从而成为数据缓存的首选存储介质。文章通过介绍SDRAM的存储体结构、主要控制时序和基本操作命令,并且结合实际系统需要,给出了一种用FPGA实现的通用SDRAM控制器的方案。通过SDRAM实现大容量的高速数据缓存具有明显的优势,而使用可编程器件实现SDRAM控制器则使之具有更高的灵活性,应用前景也十分广阔。
Among high-speed real-time or non-real-time signal processing systems, mass memory must be used for data caching. SDRAM has many advantages, making it the preferred storage medium for data caching. This paper introduces the structure of SDRAM bank, the main control timing and basic operation commands, and combined with the actual system needs, gives a FPGA implementation of a common SDRAM controller program. SDRAM to achieve large-capacity high-speed data cache has obvious advantages, and the use of programmable devices SDRAM controller makes it has a higher flexibility, the application prospects are also very broad.