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本文介绍一种简便的改进锁相环路牵引能力的方法。这种方法叫做导率障碍(derived rate rejection缩写为DRR)法,它在设备简单性和设计理论上,与使用外接自动频率控制环路的技术不同,虽然其最后结果是一致的。在通常情况下,对于锁相环路的相关检波器,DRR技术仅要求增加一个开关。加开关的方法起因于锁相环路的非线性方程及解决其相位平面问题的初浅考虑。在环路锁定后开关不影响环路的一般性能。计算机研究结果表明,对于下面的结构可获得改进: ①比例加积分控制。②比例加不完全积分控制。当初始频率误差为线性化锁相环路自然频率的5倍时,牵引时间的改进因数为2。当初始频率误差为锁相环路自然频率的10倍时,牵引时间的改进因数是10。
This article describes a simple way to improve the traction capability of a phase-locked loop. This method, called derived rate rejection (DRR), is different from a technique that uses an external automatic frequency control loop in terms of device simplicity and design theory, although the final result is consistent. Under normal circumstances, for the phase-locked loop-related detectors, DRR technology requires only one additional switch. The method of switching is due to the non-linear equation of the phase-locked loop and the primary consideration to solve the phase plane problem. The switch does not affect the general performance of the loop after the loop is locked. Computer research results show that for the following structure can be improved: Proportional plus integral control. ② proportion plus incomplete integral control. When the initial frequency error is five times the natural frequency of the linear PLL, the improvement factor for the towing time is two. When the initial frequency error is 10 times the natural frequency of the PLL, the improvement factor for the traction time is 10.