全球电子设计创新领先企业Cadence设计系统公司10月29日宣布推出一款全面的低功耗设计流程,面向基于中芯国际集成电路制造有限公司65nm工艺的设计工程师。该流程以Cadence(R)低功耗解决方案为基础,通过使用一个单一、全面的设计平台,可以更加快速地实现尖端、低功耗半导体产品的设计。“目前,功耗已成为一个关键的设计制约 Cadence Design Systems, a global leader in electronic design innovation, announced on October 29 a comprehensive low-power design flow for design engineers based at 65nm process technology from Semiconductor Manufacturing International Corp. (SMIC). The process builds on the Cadence (R) low-power solution by enabling the design of cutting-edge, low-power semiconductor products more quickly through the use of a single, comprehensive design platform. ”At present, power consumption has become a key design constraint