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随着VLSI工艺的成熟和IC开始接近ECL电路的工作速度,封装工程师面临的任务是研究符合密度和固有时间延迟这两个规范的互连方法。一些试验性的VLSI芯片已经达到每片数十万门的集成密度。封装功能的指数增加要求有更多的输入/输出端。
As the VLSI process matures and ICs begin to move closer to the speed of the ECL circuit, the packaging engineer faces the task of investigating interconnection methods that conform to both the density and inherent time delays. Some experimental VLSI chips have reached an integration density of hundreds of thousands of gates per chip. The exponential increase in package functionality requires more I / O.