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研究雷达机内自测试BIT（builtintest）的实现及雷达系统级测试．依据结构可测性设计方法，采用可编程逻辑器件设计电路板级测试单元，把芯片级边界扫描扩展到雷达系统级测试，并将该方法应用到雷达信号处理机中．给出了板级边界扫描结构和系统级测试的组成结构．雷达信号处理机系统级检测结果表明提出边界扫描测试在系统级应用是可行的．雷达系统级测试的边界扫描方法设计简单，所需硬件少，易于实现，具有在线测试、离线测试以及系统调试等功能，且故障覆盖率高，故障可定位到电路板级和芯片级．
Research Radar machine self-test BIT (builtintest) and radar system-level test. According to the design method of the structure testability, the programmable logic device is used to design the circuit board test unit, the chip level boundary scan is extended to the radar system level test, and the method is applied to the radar signal processor. The composition of board-level boundary-scan structure and system-level test is given. The system-level test results of radar signal processor show that it is feasible to propose the boundary scan test at the system level. The boundary-scan method of radar system-level testing is simple in design, less in hardware and easy to implement. It has the functions of online testing, offline testing and system debugging. The fault coverage is high and the fault can be located to the board level and the chip level.