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一种具有J—K触发器反馈电路和最大工作速度为12MC的可编程序逻辑阵列(PLA)已被设计成功,它是利用绝缘衬底上外延硅薄膜技术(ESFI)的兰宝石上硅(SOS)来实现的。文中描述了ESFI SOS技术及用以研制PLA电路的优越性,并提供了相应的研制结果。同时,一种在“与”(AND)和“或”(OR)矩阵中采用了MNOS晶体管的,具有相同数量输入、输出和反馈电路的,其功能类似于掩模程序PLA的孪生PLA亦已设计出来。这种MNOS PLA具有片上全译码功能并可编程序或个别地再编程序。提供了MNOSPLA电路并计算了器件的速度。
A programmable logic array (PLA) with a J-K flip-flop feedback circuit and a maximum operating speed of 12MC has been successfully designed using silicon on sapphire (ESFI) on an Insulator Substrate SOS) to achieve. The article describes the ESFI SOS technology and the advantages of developing PLA circuits, and provides the corresponding development results. In the meantime, a twin PLA that has the same number of input, output, and feedback circuits that uses MNOS transistors in the AND and OR matrixes that function similarly to the mask program PLA has also been used Designed. This MNOS PLA has on-chip full decoding capability and can be reprogrammed programmatically or individually. MNOSPLA circuit is provided and the speed of the device is calculated.