论文部分内容阅读
提出了一种能根据嵌入式应用系统容量的不同而灵活选择字节擦除和块擦除两种不同擦除模式的 Be NOR阵列结构 ,该结构采用沟道热电子注入进行“写”操作 ,采用分离电压法负栅压源极 F- N隧道效应进行擦除 .对分离电压法负栅压源极 F- N隧道效应擦除的研究表明 ,采用源极电压为 5 V,栅极电压为 - 10 V的擦除条件 ,不仅能很好地控制擦除后的阈值电压 ,而且当字线宽度小于等于 6 4时 ,源极电压导致的串扰效应能得到很好的抑制 .研究表明该结构具有编程速度高、读取速度高、可靠性高及系统应用灵活的特点 ,非常适宜于在 1M位以下的嵌入式系统中应用 .
A Be NOR array structure with different erasing modes of byte erase and block erase is proposed according to the capacity of embedded application system. The structure uses channel hot electron injection to write operation, The erase is performed by using the separate gate voltage source F- N tunneling effect with separate voltage method.The research on the erase effect of the negative gate F- N tunnel effect by the separation voltage method shows that the gate voltage is - The 10 V erase condition not only controls the erase threshold voltage well but also suppresses the crosstalk effect caused by the source voltage when the word line width is less than or equal to 64. Studies have shown that the structure With high programming speed, high read speed, high reliability and system flexibility, it is very suitable for embedded systems below 1 Mbit.