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利用基于复合理论的直流电流电压法,提取SOI器件背栅界面陷阱密度。给出了具体的测试原理,以0.13μm SOI工艺制造的部分耗尽NMOS和PMOS器件为测试对象,分别对两种器件的背界面复合电流进行测试。将实验得到的界面复合电流值与理论公式作最小二乘拟合,不仅可以获得背界面陷阱密度,还可以得到界面陷阱密度所在的等效能级。结果表明,采用智能剥离技术制备的SOI器件的背界面陷阱密度量级均为1010cm-2,但NMOS器件的背界面陷阱密度略大于PMOS器件,并给出了界面陷阱密度所在的等效能级。
The trap density of the back gate interface of SOI device was extracted by DC current voltage method based on compound theory. The specific test principle is given. The partially depleted NMOS and PMOS devices fabricated by 0.13μm SOI process are tested. The back-interface recombination current of the two devices is tested respectively. The experimental results of the interface current values and the theoretical formula for the least-square fitting, not only can get the back interface trap density, interface trap density can also get the equivalent energy level. The results show that the back surface trap density of the SOI devices prepared by the smart stripping technology is 1010 cm-2. However, the back surface trap density of the NMOS devices is slightly larger than that of the PMOS devices, and the equivalent energy level at the interface trap density is given.