本论文着重论述未来CMOS进入纳米尺寸的关键挑战 ,如 :电源电压和阈值电压减小、短沟效应、量子效应、杂质数起伏以及互连线延迟等影响。分析了纳米CMOS器件结构的设计 ,讨论了用于纳米尺寸的新型器件结构 ,包括SOICMOS、双栅和环栅MOSFET、凹陷沟道MOSFET、动态阈值MOSFET以及低温CMOS ,它们可能把我们带至硅器件设计的最远极限。 This dissertation focuses on the key challenges of future CMOS nanosize, such as reduction of supply voltage and threshold voltage, short-channel effects, quantum effects, fluctuations in the number of impurities and interconnect delay. The design of the nanostructured CMOS device structure is discussed and new device structures for nanometer size are discussed, including SOICMOS, double-gate and ring-gate MOSFETs, sag channel MOSFETs, dynamic threshold MOSFETs, and cryogenic CMOS that may take us to silicon devices The farthest limit of design.