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介绍了一个用于高速信号传输的低功耗锁相环.提出了一种新的开环校准方法.该校准通过上电时候进行的开环数字校准很大程度上减轻了工艺变化对电路的影响,相比以前的闭环校准方法,该方法可以显著缩短校准时间.在这个锁相环中采用了双环路的结构来获得对工艺、温度和环境变化不敏感的环路参数:例如衰减因子、相位裕度等.还设计了一种新的鉴频鉴相器,它内嵌了电平转换的功能,简化了电路.该PLL的设计通过小心的供电网络划分来降低电源噪声的耦合.设计的锁相环路在输出为1.6GHz的时候均方根抖动为3.1ps,而仅消耗约为1mA的电流.
A low-power phase-locked loop for high-speed signal transmission is presented, and a new open-loop calibration method is proposed that uses open-loop digital calibration at power-up to greatly reduce process variations on the circuit This approach can significantly reduce calibration time compared to previous closed-loop calibration methods where a two-loop architecture is used to obtain loop parameters that are insensitive to process, temperature, and environmental changes such as attenuation factor, Phase margin, etc. A new phase-frequency detector is also designed, which incorporates the function of level shifting and simplifies the circuit.The PLL design is designed to reduce the coupling of power supply noise by careful power supply network. Of the phase-locked loop jitter of 3.1ps at the output of 1.6GHz, but only consumes about 1mA of current.