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针对高职院校课程改革的要求,EDA技术课程在教学模式上发生了很大变化,本文是以“项目教学”为载体展开教学,基于Quartus Ⅱ软件、CPLD硬件平台设计了一款智能数字式竞赛抢答器案例,给出了设计分析、各模块及具体电路图。通过编辑、编译和器件编程,将编程器文件通过下载头下载到CPLD/FPGA实验板的EPM1270T144C5N器件中,经实际电路测试验证,达到了预期的设计要求。
According to the requirement of curriculum reform in higher vocational colleges, EDA technology curriculum has undergone great changes in the teaching mode. This article is based on “project teaching ” as the carrier to start teaching. Based on Quartus II software and CPLD hardware platform, a smart The digital contest responder case, given the design analysis, the module and the specific circuit. By editing, compiling and programming of the device, the programmer file is downloaded to the EPM1270T144C5N device of the CPLD / FPGA experiment board through the download head, and the actual circuit test is verified to achieve the expected design requirement.