介绍了一个采用改进型1.5位/级结构的10位100MHz流水线结构模数转换器.测试结果表明,模数转换器的信噪失真比最高可以达到57dB,在100MHz输入时钟下,输入信号为57MHz的奈奎斯特频率时,信噪失真比仍然可以达到51dB.模数转换器的差分非线性和积分非线性分别为0.3LSB和1.0LSB.电路采用0.18μm混合信号CMOS工艺实现,芯片面积为0.76mm2. A 10-bit, 100-MHz pipeline analog-to-digital converter with an improved 1.5-bit / level architecture is introduced.The test results show that the ADC achieves a maximum signal-to-interference ratio of 57dB and an input signal of 57MHz at a 100MHz input clock Of the Nyquist frequency, the SNR can still reach 51dB. The differential nonlinearity and integral nonlinearity of the ADC are respectively 0.3LSB and 1.0LSB. The circuit adopts 0.18μm mixed-signal CMOS process to achieve the chip area of 0.76mm2.