提出了一种采用现场可编程门阵列器件ＦＰＧＡ并利用窗函数法实现线性ＦＩＲ数字滤波器硬件电路的方案，并以一个十六降低通 ＦＩＲ数字滤波器电路的实现为例说明了利用 Ｘｉｌｉｎｘ 公司ＸＣ ４０００系列芯片的设计过程。设计的电路通过软件程序进行了验证和硬件仿真，结果表明电路工作正确可靠，能满足设计要求。 This paper presents a scheme of field programmable gate array (FPGA) device and the realization of linear FIR digital filter hardware circuit by using window function method. The implementation of a 16-pass reduction FIR digital filter circuit is taken as an example to illustrate the use of Xilinx XC 4000 series chip design process. The designed circuit is verified by software program and the hardware simulation results show that the circuit work correctly and reliably, can meet the design requirements.