论文部分内容阅读
采用国产的4H-SiC外延材料和自行开发的SiC双极晶体管的工艺技术,实现了4H-SiC npn双极晶体管特性。为避免二次外延或高温离子p+注入等操作,外延形成n+/p+/p/n-结构材料,然后根据版图设计进行相应的刻蚀,形成双台面结构。为保证p型基区能实现良好的欧姆接触,外延时在n+层和p层中间插入适当高掺杂的p+层外延,但也使双极晶体管发射效率降低,电流放大系数降低。为提高器件的击穿电压,在尽量实现低损伤刻蚀时,采用牺牲氧化等技术减少表面损伤及粗糙度,避免表面态及尖端电场集中,并利用SiC能形成稳定氧化层的优势来形成钝化保护。器件的集电结反向击穿电压达200 V,集电结在100 V下的反向截止漏电流小于0.05 mA,共发射极电流放大系数约为3。
The characteristics of 4H-SiC npn bipolar transistor have been realized by using the domestic 4H-SiC epitaxial material and the self-developed SiC bipolar transistor technology. In order to avoid the secondary epitaxy or high-temperature ions p + implantation and other operations, the epitaxial growth of n + / p + / p / n- structure material, and then according to the layout design of the corresponding etching, the formation of dual mesa structure. In order to ensure that the p-type base region can achieve good ohmic contact, proper high-doped p + layer epitaxy is inserted between the n + and p layers during epitaxy, but also the bipolar transistor emission efficiency is reduced and the current amplification factor is reduced. In order to improve the breakdown voltage of the device, sacrificial oxidation and other techniques are used to reduce the surface damage and roughness, to avoid the concentration of the surface state and the tip electric field, and to utilize the advantage of SiC to form a stable oxide layer to form a blunt Protection The device’s collector junction reverse breakdown voltage of 200 V, collector junction at 100 V under the reverse leakage current is less than 0.05 mA, the total emitter current amplification factor of about 3.