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固体工艺的迅速发展,出现更多的根本的限制,这将使发展变慢,甚至停止不前。一种限制是肯定无疑的,当我们降低了尺寸,从而降低存储在电路中的能量时,那就增加了电路对随机干扰的灵敏度。 最近测到了单片存储器对来自管壳及芯片自身的2射线的灵敏度。在将来宇宙射线影响可能是更大的限制。(本次会议的第一篇论文将指出) 器件尺寸也不能任意减小,例如减小至十分之一微米数量级的耗尽层宽度。这个尺寸范围内的情况将在有关N沟E/DMOSFET倒相器报告中讨论。这报告中推导出它的功率延迟乘积,性能和电源电压的基本限制。为此我们假设栅绝缘层厚度为50(?),这样正好能避免隧道效应。
The rapid development of solid processes, with more fundamental limitations, will slow or even halt development. One limitation is for sure, when we reduce the size and thus the energy stored in the circuit, it increases the sensitivity of the circuit to random disturbances. Recently, the sensitivity of monolithic memories to 2-rays from the envelope and the chip itself has been measured. In the future cosmic ray effects may be greater limits. (The first essay of this meeting will point out that the device size can not be arbitrarily reduced, for example to a depletion layer width that is on the order of tenths of microns. This size range will be discussed in the N-channel E / DMOSFET inverter report. This report deduces the basic limitations of its power delay product, performance, and supply voltage. For this reason we assume that the gate insulation thickness is 50 (?), So just to avoid the tunnel effect.