Interconnect相关论文
近年来,代表人工智能(Artificial Intelligence,AI)的神经网络技术正朝着高速低功耗的方向发展.然而,由于电子器件的固有极限,传统......
Magnetron-sputtered Mn/Co(40:60) coatings on ferritic stainless steel SUS430 for solid oxide fuel ce
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Oxidation behavior and electrical conductivity of Nb modified Ti3SiC2 as a novel interconnect for IT
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The critical dimension in Si device technology has been constantly shrunk.At the same time the aspect ratio of Cu trench......
In this study,we propose and demonstrate electroplating of Cu on graphene seed layer.Graphene will be not only as th......
The mechanical failure of solid oxide fuel cell(SOFC) components may cause cracks with consequences such as gas leakage,......
An optical implementation of CMOS/SEED optoelectronic integrated crossbar interconnection network is reported. The CMOS/......
Noise analysis and avoidance are an increasingly critical step in the design of deep sub-micron (DSM) integrated circuit......
The requirement of reduced RC delay and cross-talk for multilevel interconnect ULSI applications has enthusiastically d......
In deep submicron (DSM) integrated circuits (IC), coupling capacitors between interconnects become dominant over grounde......
采用 RL C模型来估计互连线间的耦合噪声并对模拟结果进行分析 ,在此基础上 ,提出了几种不同的算法实现了带串扰约束的集成电路布......
Surface planarity is of paramount importance in microelectronics. Chemical Mechanical Polishing (CMP) is the most viable......
提出了一种基于路径的缓冲器插入时延优化算法 ,算法采用高阶模型估计连线时延 ,用基于查表的非线性时延模型估计门延迟 .在基于路......
FIDER: A Force-Balance-Based Interconnect Delay Driven Re-Synthesis Algorithm for Data-Path Optimiza
As the feature size of integrated circuits is reduced to the deep sub-micron level or the nanometer level, the interconn......
Networks-on-chip(NoC),a new system on chip(SoC) paradigm,has become a great focus of research by many groups during the ......
We analyze the failure mechanism of W-plug via electromigration made in a 0.5-μm CMOS SPTM process.Failure occurs at th......
Repeater optimization is the key for SOC(System on Chip) interconnect delay design.This paper proposes a novel optimal m......
Based on the heat diffusion equation of multilevel interconnects,a novel analytical thermal model for multilevel nano-sc......
In this paper, on-chip interconnects are modeled as distributed parameter RLCG transmission lines, based on which the ma......
A networks-on-chip(NoC)cost-effective design method was given based on the globallyasynchronous locally-synchronous(GALS......
针对热效应导致RLC互连延时增加的现象进行了研究。提出了一种温度依赖的RLC互连延时模型。该模型可以用以量化热效应对互连延时的......
Whispering-gallery microcavity semiconductor lasers suitable for photonic integrated circuits and op
The characteristics of whispering-gallery-like modes in the equilateral triangle and square microresonators are introduc......
This paper presents a universal field programmable gate array(FPGA) programmable routing circuit,focusing primarily on a......
It is predicted that CMOS technology will probably enter into 22 nm node around 2012. Scaling of CMOS logic technology f......
Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circui......
As the feature size of the CMOS integrated circuit continues to shrink, the more and more serious scattering effect has ......
Low power on-chip interconnect technique is important for deep submicron SOC design. In this paper, a novel low swing dr......
As feature size keeps scaling down,process variations can dramatically reduce the accuracy in the estimation of intercon......
Spin-on-glass(SOG),an interlayer dielectric material applied in liquid form to fill narrow gaps in the sub-dielectric su......
Model order reduction of interconnect circuits is an important technique to reduce the circuit complexity and improve th......
A closed-form model for the frequency-dependent per-unit-length resistance of trapezoidal cross-sectional interconnects ......
An optical waveguide interconnect mesh network scheme for parallel multiprocessor systems based on an electro-optical pr......
The number of the dummy via can significantly affect the interconnect average temperature.This paper explores the modeli......
An interconnecting bus power optimization method combining interconnect wire spacing with wire order
On-chip interconnect buses consume tens of percents of dynamic power in a nanometer scale integrated circuit and they wi......
As the feature size of the CMOS integrated circuit continues to shrink,process variations have become a key factor affec......
A novel test approach for interconnect resources (IRs) in field programmable gate arrays (FPGA) has been proposed.In the......
Based on a stochastic wire length distributed model, the interconnect distribution of a three-dimensional integrated cir......
In the era of the nanometer CMOS technology, due to stringent system requirements in power, performance and other fundam......
An ultra-wideband 4 GS/s 4 bit analog-to-digital converter(ADC)which is fabricated in 2-level interconnect, 1.4μm InGaP......
The driving force for development of IC and systemin future: Reducing the power consumption andimpro
With the development of information technology, integrated circuits (IC) and system which target high performance and lo......
According to the thermal profile of actual multilevel interconnects,in this paper we propose a temperature distribution ......
A new LUT and carry structure embedded in the configurable logic block of an FPGA is proposed.The LUT is designed to sup......
The advent of HDI through the use of microvias was a critical development in extending the utility of copper interconnec......
Metallic carbon nanotubes(CNTs) have been proposed as a promising alternative to Cu interconnects in future integrated c......
To reduce the interconnect delay and improve the chip performance, three-dimensional (3D) chip emerged with the rapid in......
Semiconductor technology continues advancing,while global on-chip interconnects do not scale with the same pace as trans......
We propose a novel bias circuit,which can help a promising current-mode signaling(CMS) scheme(CMS-bias) enhance the robu......
Reduction of signal reflection along through silicon via channel in high-speed three-dimensional int
The through silicon via(TSV) technology has proven to be the critical enabler to realize a three-dimensional(3D)gigscale......
Impedance matching for the reduction of signal reflection in high speed multilevel three-dimensional
In high speed three-dimensional integrated circuits (3D ICs), through silicon via (TSV) insertion causes impedance disco......
