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本设计对免缩放因子CORDIC算法进一步改进,改进包括进一步减少迭代次数和减少双步CORDIC算法中区间折叠模块输出调整方式。将改进后的算法与免缩放因子单步算法和免缩放因子双步算法相结合,给出一种正余弦波形产生的架构。用Verilog编写RTL级实现改进后的架构代码,仿真输出与Matlab数据对比,其中正余弦误差都集中在2%以下。在Altera EP2C70F89C6芯片上做FPGA验证,时钟频率可达1000MHz。
In this design, the CORDIC algorithm with no scaling factor is further improved. The improvement includes further reducing the number of iterations and reducing the output adjustment of the interval folding module in the two-step CORDIC algorithm. Combining the improved algorithm with the one-step algorithm of no-scale factor and the two-step algorithm of no-scale factor, an architecture of sine-cosine waveform generation is given. RTL grade prepared by Verilog to achieve improved architecture code, simulation output and Matlab data, in which the cosine error are concentrated in less than 2%. Do FPGA verification on Altera EP2C70F89C6 chip, the clock frequency can reach 1000MHz.