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流水化的指令缓冲存储器通常被用于高频率处理器中,以提高取指带宽。然而,在以往的研究工作中,对流水化指令缓冲存储器的泄漏功耗问题关注较少。在工作中发现流水化的指令缓冲存储器较之传统的指令缓冲存储器能够更好的提供降低泄漏功耗的机会。通过这一观察,提出根据取指地址的要求来动态管理指令缓冲存储器中行的活动——仅仅使需要访问的行处于正常活动状态,而其他行均被控制在低电压模式下,从而大幅度降低这些行的泄漏功耗。通过模拟评测发现,该方法使流水化的指令缓冲存储器的泄漏功耗降低了77.3%,而处理器的性能损失仅为0.32%。
Streamlined instruction buffers are often used in high-frequency processors to increase fetch bandwidth. However, in the past research work, there was less attention paid to the problem of leakage power consumption in the pipelining instruction buffer memory. In the work, it is found that the streamlined instruction cache can better provide the opportunity to reduce leakage power consumption than the traditional instruction cache. Through this observation, it was proposed to dynamically manage the activity in the instruction cache according to the fetch address - a mere reduction of only the rows requiring access to normal activity while the other rows are controlled in a low-voltage mode The leakage power of these lines. Through the simulation evaluation, we found that this method reduces the drain power consumption of the shuffled instruction buffer by 77.3% while the processor performance loss is only 0.32%.