论文部分内容阅读
囿于材料和工艺稳定性等原因,纳米级集成电路制造依然基于193 nm激发光的工艺,光刻波长远大于版图尺寸,使得制造中光的干涉和衍射现象极大降低了分辨率,影响了芯片质量,因此版图在制造前需要使用可制造性模型进行查错.传统模型对制造过程进行物理建模,通过对模型中的矩阵进行分解得到卷积核,所使用的物理模型不仅复杂,而且应用难度高,加之还有物理模型缺失的情况,因此难以描述具有上千参数的生产线.本文使用卷积的形式作为可制造性模型的框架,通过优化算法提取版图到硅片轮廓这一过程的信息并以卷积核的形式体现出来,卷积核中的每一个元素均为根据已知的生产线输入输出数据优化得出,是描述制造过程的一个维度.该模型克服了传统模型需要工艺参数等机密信息的缺陷,同时具有更强的描述制造过程的能力;模型甚至可以包含版图校正信息,描述从版图到硅片轮廓这一全流程.该模型在65 nm工艺下的实验结果表明该模型具有8 nm的精度.
囿 Due to material and process stability, nano-scale integrated circuit manufacturing is still based on the 193 nm excitation light. The wavelength of the lithography is much larger than the layout size, so the interference and diffraction phenomenon of light during manufacturing greatly reduces the resolution, affecting Chip quality, so the layout in the manufacturing before the need for the use of manufacturability model to make mistakes.Traditional model of the manufacturing process of physical modeling, by decomposing the matrix in the model to get the convolution kernel, the use of the physical model is not only complex, but also It is difficult to describe the production line with thousands of parameters.This paper uses the convolution form as the framework of the manufacturability model and the optimization algorithm to extract the layout to the contour of the silicon wafer The information is presented in the form of a convolution kernel. Each element in the convolution kernel is optimized based on known input and output data of the production line and is a dimension that describes the manufacturing process. This model overcomes the fact that the traditional model requires process parameters And other confidential information defects, at the same time have a stronger ability to describe the manufacturing process; the model can even contain layout correction information, Describing the entire process from layout to silicon outline, the experimental results of the model at 65 nm show that the model has an accuracy of 8 nm.