论文部分内容阅读
为实现CCD相机高清图像数据的处理,设计了一种基于FPGA的高速桥接平台,提出硬件模块的实现方案。在FPGA内部,使用Verilog HDL对底层电路进行描述;详细阐述了基于FPGA的SATAⅡ接口管理实现方案,给出主机端上电初始化模块和设备端上电初始化模块的状态机设计;说明利用DRP(Dynamic Reconfiguration Port)使SATAⅡ接口向下兼容SATAⅠ接口的实现方法,设计了速度协商状态机。最后在实验平台上通过板级调试,固态硬盘和主机成功通讯,满足SATAⅡ接口的速度要求,可以用作高清图像处理算法的移植平台。
In order to realize the high definition image data processing of CCD camera, a high speed bridge platform based on FPGA was designed and the realization scheme of hardware module was put forward. In the FPGA, the use of Verilog HDL to describe the underlying circuit; FPGA-based SATA II interface management scheme is described in detail, the host-side power-on initialization module and device-side power-on initialization module state machine design; instructions using DRP (Dynamic Reconfiguration Port) SATA II interface backward compatible with the implementation of SATA I interface, the design of the speed negotiation state machine. Finally, through the board-level debugging on the experimental platform, the successful communication between the SSD and the host meets the speed requirement of the SATA II interface and can be used as a migration platform for the HD image processing algorithm.